There exists a method for performing adaptive filtering on a communication signal with a digital filter. In this method, a set of coefficients is used for each “run” of a digital filter, and it is determined whether an output of the digital filter obtained by using the set of coefficients is equal to a selected error level. When the output of the digital filter obtained by using the set of coefficients is not equal to the selected error level, the coefficients are adjusted until the output from the digital filter becomes equal to the selected error level, and the set of adjusted coefficients is stored in a memory. When the digital filter is run later, the set of adjusted coefficients is read from the memory and loaded into the digital filter (see, for example, Japanese Laid-Open Patent Publication No. 2000-077979).
A known 5-Gbps transceiver includes a front end employing an analog-to-digital converter (ADC). The front end extracts an input signal without adjusting the phase difference between the input signal and a sampling clock signal. Phase tracking and data determination of the input signal are performed in a computational domain (see, for example, Yamaguchi, H. “A 5 Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65 nm CMOS”, 2010 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC)).
However, with the related-art method and transceiver described above, it is difficult to detect a phase of a signal with a small phase detection error without increasing the overhead.